Driver circuitry for programmable logic devices with hierarchical interconnection resources

ABSTRACT

A programmable logic device has logic array blocks (“LABs”) and interconnection resources. For interconnecting signals to, from, and between the LABs, the global interconnection resources may include switch boxes, long lines, double lines, single lines, and half- and partially populated multiplexer regions. The LAB includes two levels of function blocks. In a preferred embodiment, there is one four-input second-level function block for every four-input first-level function blocks. At least one tri-state buffer is provided in each LAB. Each tri-state buffer may receive a data signal either from one or more function blocks in the associated LAB or from one or more interconnection conductors adjacent to the LAB. The tri-state buffer may buffer one of the received data signals and apply the resulting buffered signal to one or more of the interconnection conductors adjacent to the LAB.

This invention claims the benefit of United States provisional patentapplication No. 60/062,476, filed Oct. 16, 1997, which is herebyincorporated by reference in its entirety

BACKGROUND OF THE INVENTION

This invention relates to programmable logic devices, and moreparticularly to driver circuitry usable in programmable logic deviceswith increased logic and interconnection capability.

Programmable logic devices are well known as is shown, for example, byPedersen et al. U.S. Pat. No. 5,260,610, Cliff et al. U.S. Pat. No.5,260,611, Cliff et al. U.S. Pat. No. 5,689,195, Cliff U.S. Pat. No.5,815,726, Cliff et al. U.S. Pat. No. 5,909,126 Reddy et al. U.S. Pat.No. 5,977,793, McClintock et al. U.S. Pat. No. 5,999,016, and PedersenU.S. patent application Ser. No. 09/022,663, filed Feb. 12, 1998. All ofthese references are hereby incorporated by reference herein in theirentirety.

Programmable logic devices can include a plurality of super-regions ofprogrammable logic disposed on the device in a two-dimensional array ofintersecting rows and columns of such super-regions. Each super-regionmay include a plurality of regions of programmable logic. Each regionmay include a plurality of subregions of programmable logic. Eachsubregion may include (1) a four-input look-up table which isprogrammable to produce an output signal that is any logical combinationof the four inputs applied to the look-up table, (2) a register(flip-flop) for registering the output signal of the look-up table, and(3) circuitry for allowing the final output of the subregion to beeither the registered or unregistered output signal of the look-uptable.

Interconnection conductors are provided on the device for conveyingsignals to, from, and between the subregions in each region, as well asto, from, and between the regions and super-regions. For example,horizontal interconnection conductors may be associated with each row ofregions for conveying signals to, from, and between the regions in theassociated row. Vertical interconnection conductors may be associatedwith each column of regions for conveying signals to, from, and betweenthe rows. And local conductors may be associated with each region forconveying signals to, from, and between the subregions in that region.Programmable interconnections are provided for making connectionsbetween the various types of interconnection conductors so that signalscan be routed throughout the device in a great many different ways. Forexample, the local conductors associated with each region may beprogrammably interconnectable to the horizontal and/or verticalconductors adjacent to that region. Similarly, intersecting horizontaland vertical conductors may be programmably interconnectable.

Various kinds of drivers may be provided for driving signals from thesubregions out onto the adjacent interconnection conductors. Forexample, certain of the horizontal and vertical conductors adjacent toeach region may be driven by the output signals of that region'ssubregions via a buffer and an NMOS pass gate. Each such buffer may becapable of driving one or more horizontal and/or vertical conductors.Each pass gate is controlled by an associated static programmableelement. Alternative driver circuitry involves the use of tri-statedrivers feeding tri-state lines. The enable signal for each tri-statebuffer is generated elsewhere on the device or comes from an input pin.Thus each such enable signal must be explicitly routed to each tri-statedriver that it controls. This can result in extra delay in the enablepath and may require considerable routing resources.

In view of the foregoing, it is an object of this invention to provideimproved driver circuitry for programmable logic devices.

It is a more particular object of this invention to provide improvedtri-state-type driver circuitry for programmable logic devices.

SUMMARY OF THE INVENTION

These and other objects of the invention are accomplished in accordancewith the principles of the invention by providing a new programmablelogic device architecture with an improved logic array block (“LAB”) andimproved interconnection resources. For interconnecting signals to andfrom the LABs, the global interconnection resources may include switchboxes, long lines, double lines, single lines, and half- and partiallypopulated multiplexer regions. The LAB includes two levels of functionblocks. In a preferred embodiment, in a first level, there are eightfour-input function blocks. In a second level, there are two four-inputfunction blocks. In another preferred embodiment there are 16first-level and four second-level four-input function blocks. At leastone tri-state buffer is provided. The tri-state buffer may beprogrammably coupled to receive signals from and send signals to theLABs without passing through the global interconnection resources. Thetri-state buffer may also be programmably coupled to receive signalsfrom and send signals to the global interconnection resources. In oneembodiment, the function blocks are implemented using look-up tables(“LUTs”). The LAB may contain storage blocks for implementing sequentialor registered logic functions.

Further features of the invention, its nature and various advantageswill be more apparent from the accompanying drawings and the followingdetailed description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified plan view of a portion of an illustrativeembodiment of a programmable logic device with which this invention canbe used.

FIG. 2 is a somewhat more detailed, but still simplified, plan view ofan illustrative embodiment of a representative portion of the FIG. 1apparatus.

FIG. 3 is an even more detailed, but still simplified plan view of anillustrative embodiment of a representative portion of the FIG. 2apparatus.

FIG. 4 is a more detailed, but still simplified, schematic block diagramof an illustrative embodiment of a representative portion of the FIG. 1apparatus in accordance with this invention.

FIG. 5 is a simplified block diagram of representative portions ofanother illustrative embodiment of a programmable logic deviceconstructed in accordance with the invention.

FIG. 6 is a simplified block diagram of representative portions of stillanother illustrative embodiment of a programmable logic device which canbe constructed in accordance with the invention.

FIG. 7 is a simplified block diagram of an illustrative system employinga programmable logic device in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various aspects of the invention will first be described with referenceto embodiments of the types shown in FIGS. 1-6. Illustrative uses of theprogrammable logic devices of the invention will then be described withreference to FIG. 7.

It will be understood that terms like “row” and “column”, “horizontal”and “vertical”, “left” and “right”, “upper” and “lower”, and otherdirectional or orientational terms are used herein only for convenience,and that no fixed or absolute directions or orientations are intended bythe use of these terms. For example, the words in each of the word pairsmentioned above can be reversed if desired.

FIG. 1 is a simplified block diagram of the overall internalarchitecture and organization of a programmable logic device (“PLD”)121. Many details of PLD architecture, organization, and circuit designare not necessary for an understanding of the present invention and suchdetails are not shown in FIG. 1.

FIG. 1 shows a six-by-six two-dimensional array of thirty-six logicarray blocks (“LABs”) 200. Each LAB 200 is a physically grouped set oflogical resources that is configured or programmed to perform logicalfunctions. The internal architecture of a LAB will be described in moredetail below in connection with FIGS. 3 and 4. PLDs may contain anarbitrary number of LABs, more or less than the PLD 121 shown in FIG. 1.Generally, in the future, as technology advances and improves,programmable logic devices with even greater numbers of logic arrayblocks will undoubtedly be created. Furthermore, LABs 200 need not beorganized in a square matrix; for example, the array may be organized ina five-by-seven or a twenty-byseventy matrix of LABs.

LAB 200 has inputs and outputs (not shown) which may be programmablyconnected to a global interconnect structure, comprising an array ofglobal horizontal interconnects (“GHs”) 210 and global verticalinterconnects (“GVs”) 220. Although shown as single lines in FIG. 1 eachGH 210 and GV 220 line represents a plurality of signal conductors. Theinputs and outputs of LAB 200 are programmably connectable to anadjacent GH 210 and an adjacent GV 220. Utilizing GH 210 and GV 220interconnects, multiple LABs 200 may be connected and combined toimplement larger, more complex logic functions than can be realizedusing a single LAB 200.

In one embodiment, GH 210 and GV 220 conductors are programmablyconnectable at intersections 225 of these conductors. Moreover, GH 210and GV 220 conductors may make multiple connections to other GH 210 andGV 220 conductors. Various GH 210 and GV 220 conductors may beprogrammably connected together to create a signal path from a LAB 200at one location on PLD 121 to another LAB 200 at another location on PLD121. Furthermore, an output signal from one LAB 200 can be directed intothe inputs of one or more LABs 200. Also, using the global interconnect,signals from a LAB 200 can be fed back into the same LAB 200. In otherembodiments or the present invention, only selected GH 210 conductorsare programmably connectable to a selection of GV 220 conductors.Furthermore, in still further embodiments, GH 210 and GV 220 conductorsway be specifically used for passing a signal in a specific direction,such as input or output, but not both. For example, one or more GH 210or GV 220 conductors may be used as a dedicated input driver ordedicated clock network to drive the LABs 200 from an input pin of theintegrated circuit.

The PLD architecture in FIG. 1 further shows at the peripheries of thechip, input-output drivers 230. Input-output drivers 230 are forinterfacing the PLD to external, off-chip circuitry. FIG. 1 showsthirty-two input-output drivers 230; however, a PLD may contain anynumber of input-output drivers, more or less than the number depicted.Each input-output driver 230 is configurable for use as an input driver,output driver, or bidirectional driver. An input driver takes signalsfrom outside the chip and interfaces them to on-chip circuitry. Anoutput driver takes internal signals and interfaces them to the outsideworld. A bidirectional driver performs the functions of both an inputdriver and an output driver. In addition, a bidirectional driver has ahighimpedance mode which allows the driver to interface with abidirectional bus. In other embodiments of the present invention, a PLDmay have dedicated input drivers and dedicated output drivers, as wellas special “fast” input drivers and the like.

Like LABs 200, input-output drivers 230 are programmably connectable toadjacent GH 210 and GV 220 conductors. Using GH 210 and GV 220conductors, input-output drivers 230 are programmably connectable to anyLAB 200. Input-output drivers 230 facilitate the transfer of databetween LABs 200 and external, off-chip circuitry. For example, off-chiplogic signals from other chips may be coupled through input-outputdrivers 230 to drive one or more LABs 200. Based on these off-chipinputs and the logical functions programmed into LABs 200, LABs 200 willgenerate output signals that are coupled through the global interconnectto input-output drivers 230 for interfacing with off-chip circuitry.

FIG. 2 shows a further embodiment of an overall internal architectureand organization of PLD 121 of FIG. 1. PLD 121 of FIG. 2 includes LABs200, which are physically grouped sets of logical resources that areconfigured or programmed to perform logical functions. FIG. 2 shows sixLABs, arranged in a two-by-three matrix. However, PLD 121 may have anyarbitrary number of LABs, more or less than shown in FIG. 2.Furthermore, PLD 121 may be organized in any arbitrary format such as aten-by-twelve. The internal architecture of a LAB 200 will be describedin more detail below.

LABs 200 of FIG. 2 are programmably connectable, as described above inFIG. 1 using global interconnection resources. As in FIG. 1 the globalinterconnection resources of FIG. 2 are also organized in horizontal andvertical directions. Using these global interconnection resources, LABs200 may be programmably combined to form larger, more complex logicfunctions than are available from a single LAB. The globalinterconnection resources of FIG. 2 specifically include switch boxes310, partially populated multiplexer regions 320, half-populatedmultiplexer regions 330, horizontal long lines 340, vertical long lines350, horizontal double lines 360, and vertical double lines 370.

Furthermore, FIG. 2 shows only a portion of PLD 121. PLD 121 may alsocontain input-output drivers 230 (not shown), as in FIG. 1, forinterfacing PLD 121 with off-chip circuitry. As in FIG. 1, input-outputdrivers 230 (not shown) are programmably connectable using the globalinterconnection resources.

There are various types of interconnection resources, distinguishable onthe basis of the relative length of their segments. In particular, longlines (also known as “global lines”), including horizontal long lines340 and vertical long lines 350, are conductors which run the entirelength or width of the array. Horizontal long lines 340 extend in afirst direction of an array of LABs 200. Vertical long lines 350 extendin a second direction of the array of LABs 200.

Horizontal and vertical long lines 340 and 350 are used to programmablycouple signals across the entire PLD 121. In this fashion, multiple LABs200 may be combined to implement larger, more complex logic functions.Furthermore, long lines 340 and 350 are suitable conductors fordistributing high fan-out, time-critical control signals such as a clocksignal throughout a PLD integrated circuit with minimal timing skew.Moreover, long lines 340 and 350 may be fashioned into a bidirectional,tristatable bus. In one embodiment, PLD 121 may include long linesdedicated for a particular function, such as a dedicated clock line forrouting a clock network.

As shown in FIG. 2, LABs 200 have inputoutput lines 380 for receivingand providing logic signals. LAB input-output lines 380 includebidirectional paths, which may be programmed or configured as an inputor an output. Furthermore, LAB input-output lines 380 may includededicated inputs and dedicated outputs. Moreover, LAB input-output lines380 may include a combination of bidirectional paths, dedicated inputs,and dedicated outputs.

Using LAB input-output lines 380, horizontal and vertical long lines 340and 350 may be used to programmably couple signals to and from LABs 200in different locations of PLD 121. Specifically, long lines 340 and 350can provide input signals for a LAB 200 from other LABs 200. Long linesmay also be driven by circuitry such as input-output drivers 230 (notshown). Input-output drivers 230 may be used to programmably couple,through long lines 340 and 350, input signals from external, off-chipcircuitry and sources to LABs 200.

Specifically, in one embodiment, dedicated outputs from LAB 200, via LABinput-output lines 380, may be programmably coupled directly, withoutpassing through another global interconnection resource, to horizontallong lines 340. In addition, LAB inputoutput lines 380 may also beprogrammably coupled indirectly to horizontal and vertical long lines340 and 350 through other global interconnection resources includingdouble lines 360 and 370.

To connect to the dedicated inputs of LAB 200, long lines 340 and 350may be programmably coupled through partially populated multiplexerregion 320 (at intersections of long lines 340 and 350 and double lines360 and 370) to double lines 360 and 370. From double lines 360 and 370,signals may be programmably coupled through half-populated multiplexerregion 330, to LAB input-output lines 380 of LAB 200. In otherembodiments of the present invention, horizontal and vertical long lines340 and 350 may be programmably coupled directly to the dedicated inputsof LAB 200 or selected LABs 200.

By not providing a direct programmable input path from long lines 340and 350 to LABs 200, this reduces the amount of circuitry required inPLD 121. Overall die size of PLD 121 will be reduced without adverselyaffecting greatly the performance of the integrated circuit. Thenegative impact on performance will be minimal. For example, timing skewdifferences between different LABs 200 will be similar because the samedelay will be introduced for the input signals into LAB 200.Furthermore, there will be some increases in performance because lesscircuitry at the inputs of the LABs 200 also results in reducedparasitics such as resistances and capacitances, which tend to degradeperformance.

In addition to horizontal and vertical long lines 340 and 350, PLD 121of FIG. 2 includes double lines 360 and 370 for routing signals withinPLD 121. Like long lines 340 and 350, double lines 360 and 370 extend inthe horizontal and vertical directions of the array. Horizontal doublelines 360 extend in the first direction of the array of LABs 200.Vertical double lines 370 extend in the second direction of the array ofLABs 200. Compared to long lines 340 and 350, double lines 360 and 370support shorter, local connections between two adjacent LABs 200 withoutusing other global interconnection resources such as switch boxes 310and long lines 340 and 350. To simplify the diagram in FIG. 2, only thereferenced double lines 360 and 370 are shown bypassing switch box 310.Although not shown, other double lines in FIG. 3 also programmablycouple two adjacent LABs 200 without using switch boxes 310.

As is the case with long lines 340 and 350, double lines 360 and 370 maybe used to combine multiple LABs 200 to implement larger, more complexlogic functions. Horizontal and vertical double lines 360 and 370 areused, for example, to programmably couple, through half-populatedmultiplexer region 330, input and output signals (via LAB input-outputlines 380) of one LAB 200 to another LAB 200. This path does not passthrough switch boxes 310, horizontal long lines 340, or vertical longlines 350. Since double lines 360 and 370 provide shorter-lengthinterconnections than long lines 340 and 350, double lines 360 and 370generally have better performance characteristics than long lines 340and 350. Since long lines 340 and 350 are limited resources, usingdouble lines 360 and 370 reserves long lines 340 and 350 for logicfunctions requiring longer-length signal paths.

Double lines 360 and 370 can drive or be driven by a LAB 200 which hasLAB input-output lines 380 crossing, or intersecting, those particulardouble lines. More specifically, LAB input-output lines 380 may beprogrammably coupled to double lines 360 and 370 through half-populatedinput multiplexer region 330 at intersections of double lines and LABinput-output lines. As discussed above, long lines 340 and 350 may beprogrammably connected to double lines 360 and 370 through partiallypopulated multiplexer regions 320 at intersections of long lines anddouble lines.

Double lines 360 and 370 may be programmably coupled to other doublelines 360 and 370 via switch boxes 310, discussed below. In particular,to couple signals between more than two LABs 200, horizontal andvertical double lines 360 and 370 may be programmably coupled to oneanother via switch boxes 310, as needed, to implement a particular logicfunction.

PLD 121 may include single lines 385, which are similar to double lines360 and 370 except that these only intersect LAB input-output lines 380of one LAB 200, instead of two. For example, single lines 385 may beprogrammably coupled to other single lines 385 via switch boxes 310.Single lines 385 may drive or be driven by a LAB 200 which has LABinput-output lines 380 crossing, or intersecting, those particularsingle lines 385. In some embodiments, however, the globalinterconnection resources may not include single lines 385. Single lines385 permit flexibility in interconnecting signals and LABs 200, but formany of the logic designs programmed into PLDs, a LAB 200 must beconnected to at least one other LAB 200. In view of theseconsiderations, the circuitry and other overhead required to implementsingle lines may be excessive, leading to greater power consumption andlarger integrated circuit die sizes than necessary. Further, certaininterconnection resources such as switch boxes 310 (used to programmablycouple multiple single lines 385) may become the limiting factor in thesize of the design that may be implemented in the PLD. Therefore, aneffective, efficient PLD architecture may include double lines 360 and370, but not single lines 385.

Still further embodiments may include triple lines, quadruple lines,quintuple lines, sextuple lines, and other similar interconnectionresources. Furthermore, in other embodiments there may be special,direct and indirect, connections between LABs 200 that do not passthrough the global interconnection resources.

The illustrative structure shown in FIG. 2 can be somewhat like thecorresponding portion of the structure shown in above-mentioned Cliff etal. U.S. Pat. No. 5,689,195 (see especially FIG. 3 of that patent).However, FIG. 2 is somewhat simplified as compared to that Cliff et al.FIG. It will be understood that, if desired, additional features fromthe Cliff et al. structure can be included in regions provided in thepresent devices. Examples of such possible other features are additionalconductors for so-called fast lines and/or clock signals, carry and/orcascade interconnections between logic modules or “subregions” withinLABs, register control signals derived from local conductors, etc. Thedetailed structure of subregions can be as shown in FIG. 8 of the sameCliff et al. reference. For example, some of the features shown inMcClintock et al. U.S. Pat. No. 5,614,840, Cliff et al. U.S. Pat. No.5,541,530, Leong et al. U.S. Pat. No. 5,592,106, Reddy et al. U.S. Pat.No. 5,694,058, Pedersen U.S. Pat. No. 5,872,463 and Cliff et al. U.S.Pat. No. 5,909,126 can be employed if desired. These additionalreferences are also hereby incorporated by reference herein.

FIG. 3 shows a block diagram of a specific embodiment of LAB 200 whichis useful for the present invention. LAB 200 of FIG. 3 is configurableto implement logic functions. LAB 200 has eight “primary” programmablefunction generators. These primary programmable function generatorsinclude “primary” four-input look-up tables (“LUTs”) 601, 605, 610, 615,620, 625, 630, and 635 in a first level.

LUTs are programmable elements configurable to provide a logicalfunction. In-particular, a four-input LUT is configurable to produce thesixteen possible logical outputs for any Boolean operation of the fourvariables. Instead of a look-up table, LUTs may be designed using otherprogrammable systems for performing and/or functionality such as logicgates, flip-flops, multiplexers, and programmable AND-OR arrays.

In a preferred embodiment, LUTs are implemented using a random accessmemory (“RAM”). More specifically, LUTs are implemented using a 16-bitRAM, in one specific embodiment, each bit storing an output statecorresponding to one of, e.g., sixteen possible input combinations. Infurther embodiments of the present invention, LUTs may be implementedusing other types of memories besides a RAM, such as a first-in,first-out (“FIFO”) memory or content-addressable memory (“CAM”), or acombination of these.

A RAM may be constructed using many different fabrication technologiesincluding fuse, antifuse, ferromagnetic core, erasable programmableread-only memory (“EPROM”), and electrically erasable programmableread-only memory (“EEPROM”) technology. A RAM may also be constructedfrom dynamic random access memory (“DRAM”) or static random accessmemory (“SRAM”) technology. In a preferred embodiment of the presentinvention, the LUTs of FIG. 3 use SRAM memory.

LUTs 601, 605, 610, 615, 620, 625, 630, and 635 have four inputs, whichare for the four variables used to select a particular output for thatLUT. LUT 601 has four inputs 638; LUT 605 has four inputs 640; LUT 610has four inputs 642; LUT 615 has four inputs 644; LUT 620 has fourinputs 646; LUT 625 has four inputs 648; LUT 630 has four inputs 650;and LUT 635 has four inputs 652. These inputs form part of localinterconnect structure 510 (described above) and also a portion of LABinput-output lines 380 of FIG. 2. Signals from within and external toLAB 200 may be connected to these inputs. For example, signals fromdouble lines 360 and 370 may be programmably connected to these inputsof LAB 200.

In addition to the primary LUT inputs, the inputs to LAB 200 in localinterconnect structure 510 include eight dedicated inputs 654, 656, 658,660, 662, 664, 666, and 668. A primary four-input LUT is associated witha particular dedicated input. More specifically, dedicated inputs 654,656, 658, 660, 662, 664, 666, and 668 are associated with primary LUTs601, 605, 610, 615, 620, 625, 630, and 635, respectively. Dedicatedinputs 654, 656, 658, 660, 662, 664, 666, and 668 have multiple useswhich are described further below.

These dedicated inputs and the inputs to the LUTs of LAB 200 may beprogrammably coupled to a signal provided on local interconnectstructure 510. In one embodiment, local interconnect structure 510 is ahalf-populated multiplexer structure. In a half-populated multiplexerstructure, only half of the provided signals may be coupled to aparticular LUT input. In other embodiments, local interconnect structure510 may be a fully populated or partially populated multiplexerstructure. In a fully populated multiplexer structure, every signal maybe coupled to every-LUT input. In a partially populated multiplexerstructure, only a selected portion of the signals may be coupled to aparticular LUT input.

Conceptually, LAB 200 of FIG. 3 may be divided into two groupings ofLUTs, both groupings having substantially similar configurations andconnections between elements. In particular, LUTs 601, 605, 610, and 615form a first LUT grouping; LUTs 620, 625, 630, and 635 form a second LUTgrouping. This description will only discuss the connections for LUTs601, 605, 610, and 615 in detail, since LUTs 620, 625, 630, and 635 aresimilarly connected.

In addition to primary LUTs 601, 605, 610, 615, 620, 625, 630, and 635,the LAB embodiment shown in FIG. 3 includes six secondary functiongenerators. These secondary function generators include LUTs 670, 672,674, 676, 678, and 680 in a second level. Generally, the output signalsfrom the primary LUTs are fed, directly and indirectly, into the inputsof the secondary LUTs so that larger, more complex logical functions canbe created from the combination of primary and secondary LUTs. Analogousto the two groupings of the primary LUTs, there are preferably twogroupings of secondary LUTs. A first grouping of secondary LUTs isassociated with the first grouping of primary LUTs. Similarly, a secondgrouping of secondary LUTs is associated with the second grouping ofprimary LUTs. The first grouping contains secondary LUTs 670, 672, and674. The second grouping contains LUTs 676, 678, and 680. Thisdescription will only discuss the connections for LUTs 670, 672, and 674in detail, since LUTs 676, 678, and 680 are similarly connected.

More specifically, for the first grouping of LUTs, regarding secondarytwo-input LUT 670, an output from primary LUT 601 is directly coupled toone of two inputs to secondary two-input LUT 670. An output from primaryLUT 605 is directly coupled to another input of secondary two-input LUT670. Regarding secondary two-input LUT 674, an output from primary LUT610 is directly coupled to one of two inputs to secondary two-input LUT674. An output from primary LUT 615 is directly coupled to another inputof secondary two-input LUT 674.

The second grouping of LUTs are similarly connected. Regarding secondarytwo-input LUT 676, an output from primary LUT 620 is directly coupled toone of two inputs to secondary two-input LUT 676. An output from primaryLUT 625 is directly coupled to another input of secondary two-input LUT676. Regarding secondary two-input LUT 680, an output from primary LUT630 is directly coupled to one of two inputs to secondary two-input LUT680. An output from primary LUT 635 is directly coupled to another inputof secondary two-input LUT 680.

Secondary two-input LUTs 670, 674, 676, and 680 are used to generatelogic functions based on outputs from the specified primary LUT. Thesesecondary LUTs are used to create larger, more complex logic functionsthan are available with a single primary LUT. In particular, thesecondary LUTs facilitate the combination of multiple primary LUTs. Forexample, secondary two-input LUT 670 can be used to combine primary LUTs601 and 605 to create a larger five-input LUT for handling functions ofup to five variables. Since there are four secondary two-input LUTs 670,674, 676, and 680 in the embodiment shown in FIG. 3, four five-inputlogic functions can be implemented.

LAB 200 of FIG. 3 also includes a plurality of programmable multiplexers684. Multiplexers 684 are programmably configured to couple amultiplexer input to a multiplexer output. Programmable multiplexers 684may have an arbitrary number of inputs. In FIG. 3, multiplexers 684 aretwo-input multiplexers. Multiplexers 684 are controlled, or configured,by way of user-programmable memory cells (not shown), such as SRAM bits.Depending upon the state of such user-programmed bits, an appropriateinput of multiplexer 684 is programmably coupled to the output ofmultiplexer 684.

For the first grouping of LUTs, a multiplexer 684 programmably couplesdedicated input 654 and the output of primary LUT 601 to a first inputof secondary four-input LUT 672. A multiplexer 684 programmably couplesan output of primary LUT 605 and dedicated input 656 to a second inputof secondary four-input LUT 672. A multiplexer 684 programmably couplesan output of primary LUT 610 and dedicated input 658 to a third input ofsecondary four-input LUT 672. A multiplexer 684 programmably couples anoutput of primary LUT 615 and dedicated input 660 to a fourth input ofsecondary four-input LUT 672.

The second grouping of LUTs are similarly connected to secondaryfour-input LUT 678. Specifically, a multiplexer 684 programmably couplesdedicated input 662 and the output of primary LUT 620 to a first inputof secondary four-input LUT 678. A multiplexer 684 programmably couplesan output of primary LUT 625 and dedicated input 664 to a second inputof secondary four-input LUT 678. A multiplexer 684 programmably couplesan output of primary LUT 630 and dedicated input 666 to a third input ofsecondary four-input LUT 678. A multiplexer 684 programmably couples anoutput of primary LUT 635 and dedicated input 668 to a fourth input ofsecondary four-input LUT 678.

Secondary four-input LUTs 672 and 678 are used to generate logicfunctions based on outputs from a combination of primary LUTs anddedicated inputs. These secondary LUTs 672 and 678 are used to createlarger, more complex logic functions than are available with a singleprimary LUT. Secondary LUTs 672 and 678 facilitate the combination ofmultiple primary LUTs. For example, secondary four-input LUT 672 may beused to combine primary LUTs 601, 605, 610, and 615 to create a largersix-input LUT for handling functions of up to six variables. Since thereare two secondary four-input LUTs 672 and 678 in the embodiment shown inFIG. 3, two six-input logic functions can be implemented.

Therefore, in LAB 200 of FIG. 3, two six-input logic functions and fourfive-input logic functions (see above), and combinations of these, canbe implemented. For example, LAB 200 of FIG. 3 has eight four-input LUTs601, 605, 610, 615, 620, 625, 630, and 635; another two four-input LUTscan be implemented using dedicated inputs 654, 656, 658, 660, 662, 664,666, and 668, and secondary four-inputs LUTs 672 and 678. In particular,multiplexers 684 are configured to programmably couple dedicated inputs654, 656, 658, and 660 to secondary four-input LUT 672; and dedicatedinputs 662, 664, 666, and 668 are programmably coupled to secondaryfour-input LUT 678. In this configuration, ten four-input LUTs areavailable for use.

Primary four-input LUTs 601, 605, 610, 615, 620, 625, 630, and 635 havecombinatorial path outputs 687 and registered path outputs 689. LAB 200has eight combinatorial outputs 687 and eight registered outputs 689.Combinatorial path outputs 687 are used to output results ofcombinatorial logic functions which depend on the present input statesin some predetermined fashion; in FIG. 3, this is governed by theconfiguration information within the LUTS. Registered path outputs 689are connected to storage blocks 691. These outputs 689 are used tooutput registered or sequential logic functions which depend on both theinput states and the previous history. Registered (or sequential)functions are implemented using some form of memory circuit, includingcircuits such as registers, flip-flops, and the like.

Combinatorial outputs 687 are programmably selected using programmablemultiplexers 684. For the first grouping of LUTs, a multiplexer 684programmably couples the output of primary LUT 601 and an output ofsecondary LUT 670 to a combinatorial output 687. A multiplexer 684programmably couples the output of primary LUT 605 and an output ofsecondary LUT 672 to a combinatorial output 687. A multiplexer 684programmably couples the output of primary LUT 610 and the output ofsecondary LUT 672 to a combinatorial output 687. A multiplexer 684programmably couples the output of primary LUT 615 and an output ofsecondary LUT 674 to a combinatorial output 687.

Similarly, for the second grouping of LUTs, a multiplexer 684programmably couples the output of primary LUT 620 and an output ofsecondary LUT 676 to a combinatorial output 687. A multiplexer 684programmably couples the output of primary LUT 625 and an output ofsecondary LUT 678 to a combinatorial output 687. A multiplexer 684programmably couples the output of primary LUT 630 and the output ofsecondary LUT 678 to a combinatorial output 687. A multiplexer 684programmably couples the output of primary LUT 635 and an output ofsecondary LUT 680 to a combinatorial output 687.

Combinatorial outputs 687 form a portion of LAB input-output lines 380of FIG. 2 and are programmably connectable to the global interconnectstructure, including long lines and double lines. Furthermore, asdiscussed earlier, in one embodiment, combinatorial outputs 687 areprogrammably connectable directly, to horizontal and vertical doublelines 360 and 370. Moreover, combinatorial outputs 687 may beprogrammably connected through the global interconnect structure to LABinput-output lines 380 inputting into other LABS 200 or the same LAB 200to form more complex logical functions from a combination of LABs 200.

In the embodiment shown in FIG. 3, combinatorial outputs 687 feed backinto local interconnect structure 510 (not shown to simplify thedrawing). As discussed earlier, local interconnect structure 510 is afully, partially, or half-populated multiplexer region that allowscoupling of these combinatorial outputs 687 to the inputs. Consequently,via local interconnect structure 510, combinatorial outputs 687 may beprogrammably coupled to inputs of the primary LUTs and dedicated inputs,without using interconnect resources outside the LAB such as globalinterconnect conductors.

In LAB 200 of FIG. 3, there are eight storage blocks 691. A primaryfour-input LUT may be programmably coupled to a storage block 691 forproviding a registered output 689. In particular, for the first groupingof LUTs, a data input of storage block 691 may be programmably coupledto signals from dedicated input 654, the output of primary LUT 601, andthe output of secondary LUT 670. More specifically, a multiplexer 684programmably couples to this data input of storage block 691 signalsfrom: dedicated input 654 and the output of another multiplexer 684(discussed earlier as being coupled to combinatorial output 687), whichprogrammably selects between the output of primary LUT 601 and theoutput of secondary LUT 670. These configuration paths could have beenobtained using other circuitry such as a three-input multiplexer.However, two two-input multiplexers 684 were used in the embodiment ofFIG. 3 since one multiplexer 684 is used for combinatorial output 687.This is similarly the case for the other storage blocks 691.

Further, a data input of a storage block 691 may be programmably coupledto dedicated input 656, the output of primary LUT 605, and the output ofsecondary LUT 672. In particular, a multiplexer 684 programmably couplesto this data input of storage block 691 signals from: dedicated input656 and the output of another multiplexer 684 (discussed earlier asbeing coupled to combinatorial output 687), which programmably selectsbetween the output of primary LUT 605 and the output of secondary LUT672. A data input of a storage block 691 may be programmably coupled todedicated input 658, the output of primary LUT 610, and the output ofsecondary LUT 672. In particular, a multiplexer 684 programmably couplesto this data input of storage block 691 signals from: dedicated input658 and the output of another multiplexer 684 (discussed earlier asbeing coupled to combinatorial output 687), which programmably selectsbetween the output of primary LUT 610 and the output of secondary LUT672. A data input of a storage block 691 may be programmably coupled todedicated input 660, the output of primary LUT 615, and the output ofsecondary LUT 674. In particular, a multiplexer 684 programmably couplesto this data input of storage block 691 signals from: dedicated input660 and the output of another Multiplexer 684 (discussed earlier asbeing coupled to combinatorial output 687), which programmably selectsbetween the output of primary LUT 615 and the output of secondary LUT674.

Similarly, for the second grouping of LUTs, a data input of a storageblock 691 may be programmably coupled to dedicated input 662, the outputof primary LUT 620, and the output of secondary LUT 676. In particular,a multiplexer 684 programmably couples to this data input of storageblock 691 signals from: dedicated input 662 and the output of anothermultiplexer 684 (discussed earlier as being coupled to combinatorialoutput 687), which programmably selects between the output of primaryLUT 620 and the output of secondary LUT 676. A data input of a storageblock 691 may be programmably coupled to dedicated input 664, the outputof primary LUT 625, and the output of secondary LUT 678. In particular,a multiplexer 684 programmably couples to this data input of storageblock 691 signals from: dedicated input 664 and the output of anothermultiplexer 684 (discussed earlier as being coupled to combinatorialoutput 687), which programmably selects between the output of primaryLUT 625 and the output of secondary LUT 678. A data input of a storageblock 691 may be programmably coupled to dedicated input 666, the outputof primary LUT 630, and the output of secondary LUT 678. In particular,a multiplexer 684 programmably couples to this data input of storageblock 691 signals from: dedicated input 666 and the output of anothermultiplexer 684 (discussed earlier as being coupled to combinatorialoutput 687), which programmably selects between the output of primaryLUT 630 and the output of secondary LUT 678. A data input of a storageblock 691 may be programmably coupled to dedicated input 666, the outputof primary LUT 635, and the output of secondary LUT 680. In particular,a multiplexer 684 programmably couples to this data input of storageblock 691 signals from: dedicated input 668 and the output of anothermultiplexer 684 (discussed earlier as being coupled to combinatorialoutput 687), which programmably selects between the output of primaryLUT 635 and the output of secondary LUT 680.

Storage blocks 691 are used to store a logic state. Many differentlogical components can be used to form storage blocks 691 including,among others, memory cells, D, T, S-R, J-K, and other types of latchesand registers. For example, in the embodiment shown in FIG. 3, storageblocks 691 are D-type registers. In other embodiments of the presentinvention, LAB 200 may contain T, S-R, J-K, and other types of latchesand registers, and combinations of these. Furthermore, in anotherembodiment, storage block 691 is programmably configurable to operatealso as a transparent latch.

LAB 200 has CLK0 693, CLK1 694, CE 696, S 697, R 698, and DIN 699 inputlines. These lines govern the functionality, which are sometimesreferred to as the “secondary functions,” of storage blocks 691. Theselines form a portion of LAB input-output lines 380 (described above),which may be programmably connected to LABs, input-output drivers, orany other suitable signal sources via the global interconnectionresources, which include switch boxes 310, double lines 360 and 370, andlong lines 340 and 350.

In typical operation, storage block 691 latches in data from its datainput, and outputs data at its output 689 in response to a clock signalinput. A multiplexer 684 programmably couples a CLK0 693 signal or aCLK1 694 signal to the clock signal input of storage block 691. Theembodiment shown in FIG. 3 has eight of these multiplexers 684, whichare coupled to the clock signal inputs of storage blocks 691, onemultiplexer 684 for a storage block 691. Depending on how multiplexer684 is configured, the clock signal input of storage block 691 can becontrolled by either CLK0 693 or CLK1 694 signals. Furthermore, sincemultiplexers 684 can be programmably configured independently for theeight storage blocks 691, a portion of the registers in LAB 200 may becontrolled by CLK0 693, while the other portion is controlled by CLK1694. Eight storage blocks 691 may be also controlled by the same CLK0693 signal or CLK1 694 signal.

FIG. 4 shows an expanded view of a portion of LAB 200 of FIG. 3, inaccordance with the present invention. In particular, FIG. 4 shows agroup of five LUTs 601, 605, 610, 615, and 672, arranged in a cascadeconfiguration, as described above. The fifth LUT 672 is a cascaded LUTand can also be accessed directly from input lines 654, 656, 658, and660. A tri-statable buffer, tri-state driver 704, is driven by amultiplexer 718. Multiplexer 718 has two inputs: a first input iscoupled to receive the output of multiplexer 702 and a second input 714is coupled to receive a signal from horizontal or vertical single,double, or long lines 385, 340, 350, 360, 370 (see FIG. 2).

The control signal for tri-state driver 704 is derived from the signalprovided to output 656, also one of the same signals that can be used toaccess the fifth LUT 672. The output 716 of driver 704 can be connectedto one or more horizontal or vertical single, double, or long lines 385,340, 350, 360, 370 (see again FIG. 2), although it will be appreciatedthat the power of driver 704 tends to be needed most for driving longerlines such as 340 and 350.

The combination of driver 704 and multiplexer 718 can be used to effecta “turn” from a horizontal long line 340 to a vertical long line 350, orvice versa, or between any other types of horizontal and verticalconductors, depending on the connectivity of input 714 and output 716.

As shown in FIG. 4, multiplexer 702 is associated with a particular pairof combinatorial and registered outputs. In the embodiment shown in FIG.4, multiplexer 702 receives the combinatorial and registered outputs 687and 689 that are nominally associated with the first LUT 601. However,it should be noted that multiplexer 702 may be associated with any ofthe four pairs of combinatorial and registered outputs available in thedepicted representative portion of LAB 200. (If the multiplexer 702which supplies one of the inputs to multiplexer 718 is associated withthe first or fourth pair of outputs 687 and 689, the signal applied tothat multiplexer 718 input will be derivable only from a first-level LUT601 or 615. On the other hand, if the multiplexer 702 which supplies amultiplexer 718 input is associated with the second or third pair ofoutputs 687 and 689, the signal applied to that multiplexer 718 inputcan be derived from second level LUT 672.) In addition to multiplexer702, a multiplexer 700 can be provided. The inputs of multiplexer 700are the combinatorial and registered outputs 687, 689 that are alsoapplied to multiplexer 702. The output of multiplexer 700 can be coupledto feed back into local interconnect structure 501.

Although FIG. 4 shows only four primary LUTs 601, 605, 610, 615 and onesecondary LUT 672, it will be understood that this structure may berepeated two or more times in each LAB. For example, the circuitry shownin FIG. 5, which will next be discussed in detail, assumes that each LAB200 includes four repetitions of the FIG. 4 circuitry.

FIG. 5 shows how circuitry of the type shown in FIG. 4 can be used toenable a PLD to efficiently perform extensive signal multiplexingfunctions. For example, FIG. 5 shows PLD circuitry that can implement a32-bit bus with eight sources S1, . . . , S8. Each source S1-S8 is a rowof LABs 200, each of which includes four repetitions of circuitry of thetype shown in FIG. 4. In FIG. 5 only the tri-state drivers 704 (four ineach LAB 200) are shown (the other components of LABs 200 are omittedfor clarity). Each of four vertical long lines associated with eachcolumn of LABs can be driven by a respective one of the four tri-statedrivers 704 in each of the LABs in that column. Output enable signalsOE1, . . . , OE8 are provided via horizontal long lines 340, each outputenable signal being associated with a respective one of LAB rows S1-S8.A single output enable signal associated with any LAB row can enable all32 tri-state drivers 704 in the LABs in that row. Thus selection ofwhich of signals OE1-OE8 is output-enabling controls which of LAB rowsS1-S8 acts as the source of data signals for the 32 depicted verticallong lines 350.

FIG. 6 shows another illustrative context in which circuitry of the typeshown in FIGS. 4 and 5 can be used. In the PLD 800 shown in part in FIG.6, LABs 200 are grouped in super-regions 810 including several (e.g.,16) LABs each. Individual LABs 200 are only shown in the upper-left-mostsuper-region 810 in FIG. 8, but it will be understood that all of thesuper-regions are similarly constructed. The LABs 200 in eachsuper-region 810 are served by horizontal conductors 340 that arerelatively long and are therefore somewhat like horizontal long lines340 in FIG. 2. In addition to these conductors 340, the LABs 200 in eachsuper-region 810 are served by local conductors that are not shown inFIG. 8 but that may be similar to the local single lines 385 shown inFIG. 2. Thus local lines 385 are generally usable for conveying signalsto, from, and between individual logic modules or subregions in each LABor region 200, while conductors 340 are generally usable for conveyingsignals to, from, and between LABs in a super-region 810.

Super-regions 810 are disposed on PLD 800 in a two-dimensional array ofintersecting rows and columns of such super-regions. Horizontalinter-super-region interconnection conductors 820 are associated witheach super-region row, and vertical inter-super-region interconnectionconductors 830 are associated with each super-region column. In general,horizontal conductors 820 are usable for conveying signals to, from, andbetween the super-regions 810 in the associated row, while verticalconductors 830 are usable for conveying signals to, from, and betweenthe super-regions in the associated column. It will be appreciated thatall the various conductors that have been mentioned have uses other thanthose mentioned specifically above. For example, conductors 830 may beused for conveying signals between conductors 820 in two different rows,conductors 820 may be used for conveying signals between conductors 830in two different columns, etc.

Rather than extending uninterruptedly all the way across PLD 800, eachconductor 820 is programmably segmented at its midpoint. Thus aprogrammable tri-state driver 822 a in each conductor 820 can be used toallow the left-hand half of that conductor to drive the right-hand half.Alternatively, a programmable tri-state driver 822 b in each conductor820 can be used to allow the right-hand half of that conductor to drivethe left-hand half. As still another possibility, both of the drivers822 associated with a conductor 820 may be tri-stated, thereby allowingthe left and right halves to be used individually. The same constructionand modes of operation are provided by programmable tri-state drivers832 at the midpoint of each vertical conductor 830.

Each of LABs 200 in FIG. 6 may be constructed in accordance with thisinvention as shown in representative part in FIG. 4. In the context of aPLD architecture like that shown in FIG. 6 each LAB 200 may includeseveral (e.g., four) repetitions of the FIG. 4 circuitry. Each input 714in each LAB 200 may be connected (typically but not necessarilyprogrammably) to one or more conductors 340, 820, and/or 830 adjacent tothat LAB. Each output 716 in each LAB 200 may be connected (typicallybut not necessarily programmably) to one or more conductors 340, 820,and/or 830 adjacent to that LAB. Thus each pair of elements 704/718 ineach LAB 200 can be used to drive signals either from the LAB or fromadjacent conductors 340/820/830 onto other adjacent conductors340/820/830. For example, element pairs 704/718 can be used to makehorizontal-to-vertical or vertical-to-horizontal “turns” betweenadjacent horizontal and vertical conductors. Element pairs 704/718 canalso be used to shift signals between different levels in theinterconnection conductor hierarchy (e.g., from relatively low-levelconductors 340 to relatively high-level conductors 820/830 or viceversa).

Multiplexers structures in accordance with this invention (e.g., asshown in FIG. 5) can be readily implemented in PLD architectures of thetype shown in FIG. 6. For example, each source S1-S8 in FIG. 5 can bethe appropriate number of LABs 200 in a respective row in FIG. 6. The OEsignals in FIG. 5 can be placed on respective horizontal conductors 340and/or 820 in FIG. 6. And the multiplexer outputs (on conductors 350 inFIG. 5) can be placed on conductors 830 in FIG. 6.

FIG. 7 illustrates a programmable logic device 121 or 800 in accordancewith this invention in a data processing system 900. In addition todevice 121/800, data processing system 900 may include one or more ofthe following components: a processor 904; memory 906; I/O circuitry908; and peripheral devices 910. These components are coupled togetherby a system bus 920 and are populated on a printed circuit board 930which is contained in an end-user system 940.

System 900 can be used in a wide variety of applications, such ascomputer networking, data networking, instrumentation, video processing,digital signal processing, or any other application where the advantageof using programmable or reprogrammable logic is desirable. Programmablelogic device 121/800 can be used to perform a variety of different logicfunctions. For example, programmable logic device 121/800 can beconfigured as a processor or controller that works in cooperation withprocessor 904. Programmable logic device 121/800 may also be used as anarbiter for arbitrating access to a shared resource in system 900. Inyet another example, programmable logic device 121/800 can be configuredas an interface between processor 904 and one of the other components insystem 900. It should be noted that system 900 is only exemplary, andthat the true scope and spirit of the invention should be indicated bythe following claims.

Various technologies can be used to implement programmable logic devicesemploying this invention, as well as the various components of thosePLDs. For example, each programmable switch or multiplexer (e.g.,elements 310, 510, 684, etc.; generically referred to as programmablelogic connectors or “PLCs”) can be a relatively simple programmableconnector such as a switch or a plurality of switches for connecting anyone of several inputs to an output. Alternatively, each PLC can be asomewhat more complex element which is capable of performing logic(e.g., by logically combining several of its inputs) as well as making aconnection. In the latter case, for example, each PLC can be productterm logic, implementing functions such as AND, NAND, OR, or NOR.Examples of components suitable for implementing PLCs are EPROMs,EEPROMs, pass transistors, transmission gates, antifuses, laser fuses,metal optional links, etc. The components of PLCs can be controlled byvarious, programmable, function control elements (“FCEs”). (With certainPLC implementations (e.g., fuses and metal optional links) separate FCEdevices are not required.) FCEs can also be implemented in any ofseveral different ways. For example, FCEs can be SRAMs, DRAMs, first-infirst-out (“FIFO”) memories, EPROMs, EEPROMs, function control registers(e.g., as in Wahlstrom U.S. Pat. No. 3,473,160), ferro-electricmemories, fuses, antifuses, or the like. FCEs (made using any of thesetechnologies) can also be used to implement or control LUTs. From thevarious examples mentioned above it will be seen that this invention isapplicable to both one-time-only programmable and reprogrammabledevices.

It will be understood that the foregoing is only illustrative of theprinciples of this invention and that various modifications can be madeby those skilled in the art without departing from the scope and spiritof the invention. For example, the number of logic modules (subregions;LUTs and registers) in a LAB 200 can be varied. Similarly, the number ofLABs (regions) 200 in a super-region 810 can be varied. The number ofrows and columns of LABs 200 or super-regions 810 in a PLD can bevaried. The numbers of the various types of interconnection resourcessuch as conductors, PLCs, drivers, and the like can all be varied asdesired. Various types of programmable logic can be used in thesubregions, and various technologies can be used for the PLCs and otherelements of the device, all as suggested above.

What is claimed is:
 1. A programmable logic array integrated circuitorganized as a two-dimensional array of cells comprising: a firstplurality of conductors extending along a first dimension of saidtwo-dimensional array; a second plurality of conductors extending alonga second dimension of said two-dimensional array, said second pluralityof conductors programmably coupled to said first plurality ofconductors; and a plurality of logic array blocks, wherein a logic arrayblock comprises: a plurality of first-level programmable function blocksconfigured to implement logic functions; a second-level programmablefunction block, programmably coupled to said plurality of first-levelprogrammable function blocks, without passing through said firstplurality of conductors and said second plurality of conductors, saidsecond-level programmable function block configured to implement logicfunctions of outputs from said plurality of first-level programmablefunction blocks; tri-state buffer circuitry configured to receive datasignals from at least one of said programmable function blocks and atleast one of said conductors, and further configured to select andbuffer one of the data signals thus received and to apply that datasignal to at least one other of said conductors; and a plurality ofdedicated inputs programmably coupled to said second-level programmablefunction block.
 2. The circuit defined in claim 1 wherein said tri-statebuffer circuitry includes: a register configured to register said datasignal received from said at least one of said programmable functionblocks; and switching circuitry configured to programmably select saiddata signal received from said at least one of said programmablefunction blocks either before or after registration by said register asa signal that the tri-state buffer circuitry can buffer and apply tosaid at least one other of said conductors.
 3. The circuit defined inclaim 1 wherein said tri-state buffer circuitry includes a tri-statecontrol input terminal connected to one of said dedicated inputs.
 4. Thecircuit defined in claim 3 wherein the dedicated inputs to which thetri-state control input terminals are connected in a first subpluralityof the logic array blocks are connectable to a common one of saidconductors.
 5. The circuit defined in claim 4 wherein the at least oneof said conductors are all different for all of the logic array blocksin the first subplurality.
 6. The circuit defined in claim 5 wherein thecommon one of said conductors is selected from a first one of said firstand second pluralities of conductors, and wherein the at least oneothers of said conductors for all of the logic array blocks in the firstsubplurality are selected from a second one of said first and secondpluralities of conductors.
 7. The circuit defined in claim 4 wherein thefirst subplurality is one of a plurality of similar subpluralities, andwherein the common one of said conductors for each of saidsubpluralities is different than the common one of said conductors forall others of said subpluralities.
 8. The circuit defined in claim 7wherein the at least one other of said conductors for each of the logicarray blocks in each of said subpluralities is common for a respectivelyassociated one of the logic array blocks in each of the others of saidsubpluralities.
 9. The circuit defined in claim 8 wherein the commonones of said conductors for all of said subpluralities are selected froma first one of said first and second pluralities of conductors, andwherein the at least one others of said conductors for all of the logicarray blocks in all of said subpluralities are selected from a secondone of said first and second pluralities of conductors.
 10. A digitalprocessing system comprising: processing circuitry; a memory coupled tosaid processing circuitry; and a programmable logic array integratedcircuit as defined in claim 1 coupled to the processing circuitry andthe memory.
 11. A printed circuit board on which is mounted aprogrammable logic array integrated circuit as defined in claim
 1. 12.The printed circuit board defined in claim 11 further comprising: amemory mounted on the printed circuit board and coupled to the memorycircuitry.
 13. The printed circuit board defined in claim 11 furthercomprising: processing circuitry mounted on the printed circuit boardand coupled to the memory circuitry.